1. Work closely with IC design engineers and system engineers to understand module and chip design specifications. Responsible for writing the RTL and netlist related verification documents of project based on chip architecture , and responsible for developing digital circuit module-level and system-level verification schemes
2. Able to develop a verification platform, and use Verilog, System Verilog, UVM/OVM/VMM verification methodology and other hardware design verification languages/tools, familiar with the assertion-based verification method SVA, able to achieve efficient chip functions, and perform module and SoC system-level verification work
3.Able to generate test plans according to project requirements, generate code and function coverage, and write verification reports
4. Verify the environment and validation script tools (Shell/Perl/Tcl/Makefile) and maintain the verification process to work with chip design engineers to find fixes for design flaws
5. Able to independently complete RTL-level simulation and gate-level timing (with anti-standard) simulation to execute verification and debugging for Tape Out.
1. Bachelor's degree or above in electronic engineering with at least3 years of work experience;
2. Familiar with the digital circuit verification process;
3. Familiar with the digital IC design process, familiar with UVM/VMM/OVM verification methodology, and proficient in Verilog or System Verilog/SVA hardware design verification language
4. Familiar with the Linux working environment, proficient in using scripting languages for design tools and environment development such as Makefile, Perl, Shell, TCL, etc
5. Proficiency in EOA logic simulation tools
6. Familiar with the assertion-based verification method, be able to generate a test plan according to the project requirements, generate code and function coverage, and be familiar with the netlist level with anti-standard simulation verification and debugging
7. Proficiency in the use of simulation and debugging tools such as VCS, NCSIM, Verdi, etc
8. Mixed digital and analog verification experience , able to build a mixed simulation verification platform and complete debugging, able to build FPGA platform verification and debugging with flexible software and hardware verification methods for product verification
9. Familiar with at least one version management tool: SVN, GIT;
10. Have strong learning ability, communication skills and good teamwork spirit, and excellent independent analyzing and problem solving ability.
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