1. Work closely with IC design engineers and system engineers to understand module and chip design specifications. According to the set chip architecture, responsible for writing RTL and netlist related verification documents of chip projects, and responsible for developing digital circuit module-level and system-level verification schemes 2. Develop verification platform, use Verilog, System Verilog, UVM/OVM/VMM verification methodology, and other hardware design verification languages/tools, familiar with assertion verification method SVA, realize high-efficiency chip functions, and perform module and SoC system level verification
3. Ability to generate test plans based on project requirements, generate code and functional coverage, and write verification reports 4. Verification environment and verification script tool (Shell/Perl/Tcl/Makefile), and maintain verification process, cooperate with chip design engineers to find and repair design defects 5.Ability to independently complete RTL-level simulation and gate-level timing (with anti-standard) simulation to complete verification execution and Debug to meet Tape Out requirements.
1. Bachelor degree or above in electronic engineering, three years or more experience;
2. Familiar with digital circuit verification process; 3. Familiar with digital IC design process, familiar with UVM/VMM/OVM verification methodology, proficient in Verilog or System Verilog/SVA hardware design verification language
4. Familiar with Linux working environment, proficient in using scripting language for design tools and environment development such as Makefile, Perl, Shell, TCL, etc.
5. Proficient in Cadence, Synopsys, Mentor logic simulation tools
6. Familiar with the assertion-based verification method, able to generate test plans according to project requirements, generate code and function coverage, and be familiar with netlist-level simulation verification and debugging with anti-standard
7. Skilled use of simulation and debugging tools, such as VCS, NCSIM, Verdi, etc.
8. Experience in digital and analog mixed verification, able to build a mixed simulation verification platform and complete debugging; able to build FPGA platform verification and debugging, flexibly cooperate with software and hardware verification methods and apply to product verification
9. Familiar with a version management tool: SVN, GIT;
10. Have strong learning ability, communication ability and good teamwork spirit, excellent ability to analyze and deal with problems independently.